This invention relates to a method and apparatus for transmitting binary digital data over partial-response channels. More particularly, it relates to a method and apparatus for improving the performance of a partial-response maximum likelihood detector through the use of fixed Block Digital Sums (BDS) codes.
The use of Partial-Response-Maximum-Likelihood signaling, hereinafter referred to as "PRML," is well known in the art as a means of ensuring accurate data transmission. There is, however, continuous work being done to improve the accuracy of data communication channels. For example, U.S. Pat. No. 5,414,737 discloses a data decoding device which eliminates the need for encoding by a decoder for estimating an error rate and can estimate, based on a discriminator output, the error rate at a high precision even if an error is included in the discriminator output. A square error sum is calculated by an error calculator based on an output of an equalizer. An estimated error rate is determined based on the error sum, a likelihood is determined based on the estimate error rate and soft discrimination decoding is made based on the likelihood and the output of the equalizer.
Similarly, as compressed digital television evolves, the need for being able to detect and correct errors becomes more important. An example of the application of Viterbi PRML decoders to perform such functions in digital television is disclosed in U.S. Pat. No. 5,497,401.
The continually expanding market for personal computers, in both home applications and business applications, has increased the demand for program and data storage capacities. This demand is being met by hard disc manufacturers who store the data onto magnetic films deposited on rotating hard discs. PRML signaling is used in the read channel for these hard discs. An example of such a system is disclosed in U.S. Pat. No. 5,341,387 wherein a Viterbi detector for a PR4, ML data channel includes a data sample input for receiving digital data samples from a source. Digital data samples are taken of data which has been coded in a predetermined data code format and which has been passed through a data degrading channel. A delay circuit delays the digital data samples received at the data sample input. A data selector controls an output of the delayed circuits in accordance with a feedback control bit value. An adder circuit combines data samples from the data sample input with delayed samples from a delayed circuit to produce a sum. A threshold input receives programmable positive and negative data threshold values. A threshold selector puts out either the positive or negative threshold value in accordance with a sign bit control value. A comparator compares the sum with a selected threshold value and puts out a logical value based upon comparison thereof. It includes Viterbi decision state logic for determining the sign bit control value, the feedback control bit value, and two wrong data bits for each incoming data sample. A memory path circuit decodes a sequence of consecutive values of the wrong data bits in accordance with a predetermined maximum likelihood trellis decode logic table related to the predetermined data code format and puts out a sequence of detected coded bits.
An example of the search for an optimum Viterbi detector is provided in U.S. Pat. No. 5,485,472 in which there was disclosed a method for constructing trellis codes and an apparatus for providing trellis codes with increased minimum distance between output sequences of partial-response channels with constrained inputs. A Viterbi detector expands a conventional trellis structure for the channel incorporating additional states interconnected such that a pre-selected function associates each state in the trellis with an algebraic evaluation of a polynomial at a particular element of a finite field. The detector trellis is time varying such that only certain values of the pre-selected function are allowed every M bits. The time varying assures that there are no minimum distance extensions of erroneous sequences beyond a predetermined length in the trellis. Reliability of storage channels is desirably increased because more noise is required to overcome the additional distance and cause an error in distinguishing the correct encoded sequence.
The system above, however, can be unduly complex, especially for high rate codes and channels with large memory length. It is thus desirable to reduce the complexity of the detector at a modest expense to performance.